RTHS - Real-Time Hardware Sorter

We proposed a novel multi-dimensional sorting algorithm and its related FPGA-based architecture to greatly reduce the required resources, increase memory efficiency and have little negative impact on execution time in the FPGA chip, even as the number of input records increases.

These features make our solution a worthy replacement for other sorting techniques. The proposed method can also be used for two further applications: implementing Min/Max queues to find minimum and maximum records quickly, and finding the largest or smallest records in stream processing of big data.

In the latter case we have access to the largest and smallest records at any time during the sorting process. The hardware description provided in this repository is a simple version of the RTHS design that can sort sixteen input records - a 4 × 4 matrix.