Conference papers 2020First author
3D-Sorter: 3D Design of a Resource-Aware Hardware Sorter for Edge Computing Platforms Under Area and Energy Consumption Constraints
Authors:A. NorollahZ. KazemiD. Hély
3D-Sorter is a hardware sorting architecture built on our multidimensional sorting algorithm. It arranges the input records as a three-dimensional matrix and sorts each dimension in a few phases using partial sorting, instead of comparing everything at once. The goal is a sorter small and frugal enough for edge components. The paper shows how it compares with the best hardware sorters of the time in logic, registers and power.
- Venue
- IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
- Reference
- 2020, pp. 42–47
- Topics
- sorting, 3-D design, edge computing