Journal articles 2022First author

Hardware Support for Efficient and Low-Power Data Sorting in Massive Data Application: The 3-D Sorting Method

Authors:A. NorollahZ. KazemiH. BeitollahiD. Hély

A hardware sorter speeds up data-heavy applications, but it eats into the resources of an FPGA, which are limited to begin with. ULP-Sorter is a three-dimensional sorting architecture based on our multidimensional sorting algorithm, designed for very low power and a small footprint. It targets edge devices, where both power and chip area are tight. Read the paper to see how much it saves compared with earlier hardware sorters.