Conference papers 2019First author

A New Hardware Accelerator for Data Sorting in Area & Energy Constrained Architectures

Authors:A. NorollahH. BeitollahiA. Patooghy

FPGA sorting accelerators beat general-purpose processors and GPUs, but every extra input adds compare-and-swap units, and some applications simply do not have the resources to spare. This paper presents a sorting architecture that uses unary processing to need far fewer resources while still delivering the performance the application needs. The numbers for an 8-input sorter are in the paper.